The present invention is directed generally to digital video signal processing employing an integrated decode system chip, and more particularly, to a versatile external graphics/video (EGV) port for an integrated decode system chip. The EGV port comprises a predefined number of signal input/output (I/O) pins and a dynamically configurable port controller which provides multiple connection configurations to one or more of an external graphics controller, an external digital display generator circuit and an external digital multi-standard decoder.
Multiple functions are today commonly being integrated onto a single system chip. Unfortunately, once architecture for integration of several discrete components onto a single chip is defined, functionality of the chip is necessarily limited by the components thereof. Therefore, in order to enhance adaptability of an integrated system chip, such as a digital video decode system chip for use in a set top box or digital video disc player, it may be desirable to allow for external functions to be coupled to the integrated system chip, to either enhance or replace an existing component of the system chip or add new capability to the system chip.
In a highly integrated digital video decode system chip, a significant amount of function must be brought out on as few a pins as possible. The driving factor for this is the extremely competitive environment of today""s consumer electronics market, which demands attention to the cost of the module packaging and to providing the highest VLSI integration achievable by reducing the component count for the resultant printed circuit board. As one example, Plastic Quad Flat Package (PQFP) packaging for a video decode system chip today often employs 240 pins, with a maximum of 208 signal input/output pins. Alternatively, many inexpensive printed circuit board manufacturers"" equipment will only handle PQFP packaging with 208 pins, which has a maximum of 174 signal I/O pins. Therefore, in order to integrate enhanced functionality into, for example, a digital video decode system controller chip having 240 pins or 208 pins, careful attention must be given to the number of pins needed to integrate the externally provided function(s).
Additionally, current graphics functions provided with integrated video decode system chips often only meet very low-end requirements for low cost or non-interactive digital video set-top boxes (STBs). Thus, a means to upgrade the STB graphics capabilities is believed desirable. However, the printed circuit board manufacturers again demand packages with as few pins as possible, such as PQFP packages with 208 I/O pins, or 240 pins. Within such packages, the signal I/O count is typically already at the package limit and the gate count (i.e., silicon area) is already in the degraded yield portion of the curve for current technology. These factors together do not allow for any functional graphics upgrade within the integrated video decode system chip design which would raise the cost of the chip beyond what the low end of the market is willing to pay.
In view of the above, a need exists in the art for an adaptable external graphics/video port which allows connection of an external graphics controller, for example, to either replace or supplement the integrated graphics support on chip. Additionally, it is herein deemed desirable for an analog video channel to be able to be blended with either output from an external graphics controller or an internal graphics controller or a combination thereof. These functions, as well as others described herein, must be implementable with no or minimal impact on current pin count and an absolute minimum of glue logic on the printed circuit board to provide a least expensive solution. The present invention is directed to meeting these needs.
Briefly summarized, the present invention comprises in one aspect an external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit. The EGV port comprises receiver/driver circuitry for accommodating a plurality of input/output signals, and a programmable port controller. The programmable port controller is adapted to be coupled between the receiver/driver circuit and at least one internal bus of the video decode system chip coupled to at least one of the video decoder and to the internal digital display generator circuit. The programmable port controller is programmable to either receive data into the video decode system chip for forwarding to at least one of the video decoder and the internal digital display generator circuit or to send data out from the video decode system chip from at least one of the video decoder and the internal digital display generator circuit. The data is received through or sent out through the receiver/driver circuitry of the EGV port.
In another aspect, the present invention comprises a programmable bi-directional external graphics/video (EGV) port for a video decode system chip having a video decoder and an internal digital display generator circuit. The EGV port includes a plurality of signal input/output (I/O) receiver/drivers, and a programmable port controller. The programmable port controller is coupled to the plurality of I/O receiver/drivers and to at least one internal bus of the video decode system chip. The at least one internal bus is coupled to at least one of the video decoder and the internal digital display generator circuit. The programmable port controller comprises first programmable logic for receiving video pixel data on chip or sending video pixel data off chip and second programmable logic for independently receiving on chip or sending off chip synchronization signal(s) for the video pixel data, wherein the first programmable logic and the second programmable logic allow independent outputting of pixel data from the chip while inputting synchronization signal(s) to the chip, and allow for independent inputting of video pixel data to the chip while outputting synchronization signal(s) from the chip. restate, provided herein is a multi-use, configurable video and graphics port for an integrated video decode chip. The multi-use port described herein allows a minimal amount of pins to be used for any of several possible connection configurations, and enables the blending of video from either an integrated MPEG video decoder (MVD) or an external digital multi-standard decoder (DMSD), with graphics from either or both an external graphics controller (EGPH) or an integrated on-screen display generator (OSD), and the driving of either or both an internal digital video encoder (IDENC) or an external digital video encoder (EDENC).
Numerous configurations employing the EGV port presented herein are depicted in the drawings and described below. These configurations include:
Transmission of video data through the external graphics/video port to an external digital video encoder;
Transmission of video data through the external graphics/video port to an external graphics controller chip where the video may be mixed or blended with graphics and then to an external digital video encoder;
Receipt of digital video output from a DMSD signal received through the external graphics/video port for forwarding to an internal digital video encoder;
Receipt of an analog video signal through the DMSD where the analog video is digitized and sent to the external graphics/video port to the video decorder where it may be mixed or blended with the internal graphics and then sent to the internal digital video encoder;
Forwarding of graphics from the external graphics controller through the external graphics/video port to the video decoder, with resultant blended video and graphic data forwarded to the internal digital video encoder; and
Receipt of a signal through the DMSD, forwarding to the external graphics controller for presentation to the video decoder through the external graphics/video port and hence output through the internal digital video encoder.
Video information must be synchronized to a single source or significant buffering and synchronization logic will be required forcing increased production costs. The EGV port presented herein provides the flexibility to synchronize all devices, (i.e., the IDENC, EDENC, EGPH, MVD, OSD, and DMSD) to any one of the following devices ensuring that the added production costs of buffering is not required for any of the listed configurations: DMSD, EDENC, EGPH and IDENC.
Advantageously, the EGV port of the present invention is a multi-use port, which in one embodiment, comprises a single 12-pin interface that allows:
External graphics upgrading without glue logic or additional digital display generator circuitry.
Internal DENC isolated testing for macrovision certification.
Blending graphics on an analog channel equivalent to a digital channel""s graphics capability without requiring an external (additional) DENC.
Blending upgraded external graphics with an analog and digital channel utilizing an external DENC.
Adding additional graphics plane(s) to an integrated video decoder""s existing graphics capability, maintaining software compatibility for base graphics function.